摘要
雷达在多目标检测中采用有序恒虚警率(OS-CFAR)检测器具有更好的抗干扰能力。本文根据OS-CFAR检测器原理,设计了一种基于FPGA实现方案,利用FPGA面积换取速度的设计思想,采用并行比较的方法,解决了排序耗时长的问题,实现对所有点进行检测,通过仿真验证了设计的正确性。
The radar uses an ordered constant false alarm rate(OS-CFAR) detector for multi-target detection with better anti-interference ability. According to the principle of OS-CFAR detector, this paper designs a design scheme based on FPGA, which uses the design idea of FPGA area exchange speed. It adopts the parallel comparison method to solve the problem of long sorting time, realizes detection of all points, and through simulation. Verifies the correctness of the design.
引文
[1]何友,关键,彭应宁.雷达自动检测与恒虚警处理[M].北京:清华大学出版社,1999.
[2]LONGO M, LOPS M. OS-CFAR thresholding in decentralized radar systems[C].//IEEE Transaction on Aerospace and Electronics Systems,2006,32(4):1257-1267.
[3] ROHLING H.Radar CFAR thresholding in clutter and multiple target situations[J]. IEEE Transaction on Aerospace and Electronics Systems, 1983,AES-19(4):608-620.
[4]包敏.线性调频连续波雷达信号处理技术研究与硬件实现[D].西安电子科技大学, 2009.
[5]高亚军,张冠杰,陈矛.基于FPGA的CFAR设计与实现[J]火控雷达技术2006 35 64-67.
[6]刘中祥,宋志勇,付强.基于FPGA的二维OSCFAR设计与实现[J]全球定位系统2015 5 76-80.