高阈值电压低界面态增强型Al_2O_3/GaN MIS-HEMT
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摘要
采用高温热氧化栅极凹槽刻蚀工艺并结合高温氮气氛围退火技术,制备出了高阈值电压的硅基GaN增强型Al_2O_3/GaN金属-绝缘体-半导体高电子迁移率晶体管(MIS-HEMT)。采用高温热氧化栅极凹槽刻蚀工艺刻蚀AlGaN层,并在AlGaN/GaN界面处自动终止刻蚀,可有效控制刻蚀的精度并降低栅槽表面的粗糙度。同时,利用高温氮气退火技术能够修复Al_2O_3/GaN界面的界面陷阱,并降低Al_2O_3栅介质体缺陷,因此能够减少Al_2O_3/GaN界面的界面态密度并提升栅极击穿电压。采用这两项技术制备的硅基GaN增强型Al_2O_3/GaN MIS-HEMT具有较低的栅槽表面平均粗糙度(0.24 nm)、较高的阈值电压(4.9 V)和栅极击穿电压(14.5 V)以及较低的界面态密度(8.49×10~(11) cm~(-2))。
GaN E-mode Al_2O_3/GaN metal-insulator-semiconductor high electron mobility transistors(MIS-HEMTs) with high threshold voltage were fabricated on Si substrate by using high-temperature thermal oxidation gate etching process and high-temperature nitrogen atmosphere annealing technique. The AlGaN layer was etched by using the high-temperature thermal oxidation gate etching process, which could be self-terminated at the AlGaN/GaN interface. And it could effectively control the etching accuracy and reduce the surface roughness. Simultaneously, the interface traps of the Al_2O_3/GaN interface were repaired by using high-temperature nitrogen annealing technology, and the body defects of Al_2O_3 gate dielectric were reduced. Therefore, the interface state density of the Al_2O_3/GaN interface was reduced and the gate breakdown voltage was increased. The GaN E-mode Al_2O_3/GaN MIS-HEMT fabricated on Si substrate by these two technologies has the advantages of lower surface average roughness(0.24 nm), higher threshold vol-tage(4.9 V),gate breakdown voltage(14.5 V) and lower interface state density(8.49×10~(11) cm~(-2)).
GaN E-mode Al_2O_3/GaN metal-insulator-semiconductor high electron mobility transistors(MIS-HEMTs) with high threshold voltage were fabricated on Si substrate by using high-temperature thermal oxidation gate etching process and high-temperature nitrogen atmosphere annealing technique. The AlGaN layer was etched by using the high-temperature thermal oxidation gate etching process, which could be self-terminated at the AlGaN/GaN interface. And it could effectively control the etching accuracy and reduce the surface roughness. Simultaneously, the interface traps of the Al_2O_3/GaN interface were repaired by using high-temperature nitrogen annealing technology, and the body defects of Al_2O_3 gate dielectric were reduced. Therefore, the interface state density of the Al_2O_3/GaN interface was reduced and the gate breakdown voltage was increased. The GaN E-mode Al_2O_3/GaN MIS-HEMT fabricated on Si substrate by these two technologies has the advantages of lower surface average roughness(0.24 nm), higher threshold vol-tage(4.9 V),gate breakdown voltage(14.5 V) and lower interface state density(8.49×10~(11) cm~(-2)).
引文
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[12] WANG Y,WANG M J,XIE B,et al. High-performance normally-off Al2O3/GaN MOSFET using a wet etching-based gate recess technique [J]. IEEE Electron Device Letters,2013,34(11):1370-1372.
[13] HWANG I J,KIM J,CHOI H S,et al. p-GaN gate HEMTs with tungsten gate metal for high threshold voltage and low gate current [J]. IEEE Electron Device Letters,2013,34(2):202-204.
[14] WANG Y H,LIANG Y C,SAMUDRA G S,et al. 6.5 V high threshold voltage AlGaN/GaN power metal-insulator-semiconductor high electron mobility transistor using multilayer fluorinated gate stack [J]. IEEE Electron Device Letters,2015,36(4):381-383.
[15] ZHOU Q,LIU L,ZHANG A B,et al. 7.6 V threshold voltage high-performance normally-off Al2O3/GaN MOSFET achieved by interface charge engineering [J]. IEEE Electron Device Letters,2016,37(2):165-168.
[2] SHI Y J,HUANG S,BAO Q L,et al. Normally off GaN-on-Si MIS-HEMTs fabricated with LPCVD-SiNx passivation and high-temperature gate recess [J]. IEEE Transactions on Electron Devices,2016,63(2):614-619.
[3] CHEN K J,HABERLEN O,LIDOW A,et al. GaN-on-Si power technology: devices and applications [J]. IEEE Transactions on Electron Devices,2017,64(3):779-795.
[4] CHEN W J,WONG K Y,CHEN K J. Single-chip boost converter using monolithically integrated AlGaN/GaN lateral field-effect rectifier and normally off HEMT [J]. IEEE Electron Device Letters,2009,30(5):430-432.
[5] WONG K Y,CHEN W J,CHEN K J. Characterization and analysis of the temperature-dependent on-resistance in AlGaN/GaN lateral field-effect rectifiers [J]. IEEE Tran-sactions on Electron Devices,2010,57(8):1924-1929.
[6] AMBACHER O,SMART J, SHEALY J R,et al. Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN/GaN heterostructures [J]. Journal of Applied Physics,1999,85(6):3222-3233.
[7] CAI Y,ZHOU Y G,CHEN K J,et al. High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment [J]. IEEE Electron Device Letters,2005,26(7):435-437.
[8] CHAO C,LIU X Z,TIAN B L,et al. Fabrication of enhancement-mode AlGaN/GaN MISHEMTs by using fluorinated Al2O3 as gate dielectrics [J]. IEEE Electron Device Letters,2011,32(10):1373-1375.
[9] LANFORD W B,TANAKA T,OTOKI Y,et al. Recessed-gate enhancement-mode GaN HEMT with high threshold voltage [J]. Electronics Letters,2005,47(1):449-450.
[10] IM K S,HA J B,KIM K W,et al. Normally off GaN MOSFET based on AlGaN/GaN heterostructure with extremely high 2DEG density grown on silicon substrate [J]. IEEE Electron Device Letters,2010,31(3):192-194.
[11] GAO J N,JIN Y F,HAO Y L,et al. Gate-recessed normally off GaN MOSHEMT with high-temperature oxidation/wet etching using LPCVD Si3N4 as the mask [J]. IEEE Transactions on Electron Devices,2018,65(5):1728-1733.
[12] WANG Y,WANG M J,XIE B,et al. High-performance normally-off Al2O3/GaN MOSFET using a wet etching-based gate recess technique [J]. IEEE Electron Device Letters,2013,34(11):1370-1372.
[13] HWANG I J,KIM J,CHOI H S,et al. p-GaN gate HEMTs with tungsten gate metal for high threshold voltage and low gate current [J]. IEEE Electron Device Letters,2013,34(2):202-204.
[14] WANG Y H,LIANG Y C,SAMUDRA G S,et al. 6.5 V high threshold voltage AlGaN/GaN power metal-insulator-semiconductor high electron mobility transistor using multilayer fluorinated gate stack [J]. IEEE Electron Device Letters,2015,36(4):381-383.
[15] ZHOU Q,LIU L,ZHANG A B,et al. 7.6 V threshold voltage high-performance normally-off Al2O3/GaN MOSFET achieved by interface charge engineering [J]. IEEE Electron Device Letters,2016,37(2):165-168.