用于电荷域流水线ADC的1.5位子级电路
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摘要
针对高速高精度模数转换器的性能依赖于高增益带宽积运放而导致较大功耗的问题,提出了一种基于斗链式电荷器件的电荷域流水线1.5位子级电路.该子级电路使用增强型电荷传输电路来实现电荷传输和余量电荷计算,去除了传统流水线模数转换器中的高性能运放,可大大降低模数转换器的功耗.基于所提出的1.5位子级电路,在0.18μm CMOS工艺条件下,设计了一款10位、250MS/s电荷域流水线模数转换器.测试结果表明,该模数转换器样片在全速采样时对于9.9MHz正弦输入信号转换得到的无杂散动态范围为644dB,信噪失真比为56.9dB,而功耗为45mW.
A 1.5bit sub-stage circuit based on bucket-brigade devices(BBD)for high speed charge domain pipelined ADCs is presented to solve the problem that the performances of high-speed,high-resolution ADCs rely on the opamps with large gain-bandwidth production,which results in large power consumption.Charge transfer and residue charge calculation are realized with a boosted charge transfer(BCT)circuit in the proposed 1.5bit sub-stage,and therefore,the high-performance opamps in traditional pipelined ADCs are eliminated and the power consumption can be reduced remarkably.Based on the proposed 1.5bit substage circuit,a 10 bit 250MS/s charge domain pipelined ADC is designed in 0.18μm CMOS technology.Measurement results under a sampling frequency of 250 MHz and an input sinusoidal frequency of 9.9MHz show that the ADC achieves a spurious free dynamic range(SFDR)of 64.4dB and a signal-to-noise-anddistortion ration(SNDR)of 56.9dB,with power consumption of only 45 mW.
A 1.5bit sub-stage circuit based on bucket-brigade devices(BBD)for high speed charge domain pipelined ADCs is presented to solve the problem that the performances of high-speed,high-resolution ADCs rely on the opamps with large gain-bandwidth production,which results in large power consumption.Charge transfer and residue charge calculation are realized with a boosted charge transfer(BCT)circuit in the proposed 1.5bit sub-stage,and therefore,the high-performance opamps in traditional pipelined ADCs are eliminated and the power consumption can be reduced remarkably.Based on the proposed 1.5bit substage circuit,a 10 bit 250MS/s charge domain pipelined ADC is designed in 0.18μm CMOS technology.Measurement results under a sampling frequency of 250 MHz and an input sinusoidal frequency of 9.9MHz show that the ADC achieves a spurious free dynamic range(SFDR)of 64.4dB and a signal-to-noise-anddistortion ration(SNDR)of 56.9dB,with power consumption of only 45 mW.
引文
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[7]MIYAHARA Y,SANO M,KOYAMA K.et al.A 14b60MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity[J].IEEE Journal of Solid-state Circuits,2014,49(2):416-425.
[8]SEPKE T,FIORENZA J K,SODINI C G,et al.Comparator-based Switched-capacitor Circuits for Scaled CMOS Technologies[C]//Digest of Technical Papers-IEEE International Solid-state Circuits Conference.Piscataway:IEEE,2006:220-221.
[9]BROOKS L,LEE H S.A Zero-Crossing-Based 8-bit 200MS/s Pipelined ADC[J].IEEE Journal of Solid-state Circuits,2007,42(12):2677-2687.
[10]BERGLUND C N.Analog Performance Limitations of Charge Transfer Dynamic Shift Registers[J].IEEE Journal of Solid-state Circuits,1971,6(6):391-394.
[11]ANTHONY M,KOHLER E,KURTZE J,et al.A Process-scalable Low-power Charge-domain 13-bit Pipeline ADC[C]//IEEE Symposium on VLSI Circuits-Digest of Technical Papers.Piscataway:IEEE,2008:212-213.
[12]CHEN Z H,HUANG S R,ZHANG H,et al.A 27-mW 10-bit 125-MSPS Charge-domain Pipelined ADC with PVT Insensitive Boosted Charge Transfer[J].Journal of Semiconductors,2013,34(3):035009.
[13]CHEN Z H,QIAN H W,HUANG S R,et al.Low Power Time-interleaved 10-bit 250MSPS Charge Domain Pipelined ADC for IF Sampling[J].Journal of Semiconductors,2013,34(6):065005.
[14]SHIN C S,AHN G C.A 10-bit 100-MS/s Dual-channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique[J].IEEE Transactions on Circuits and Systems II:Express Briefs,2011,58(5):274-278.
[2]PAYNE R,CORSI M,SMITH D,et al.A 16-Bit 100to 160MS/s SiGe BiCMOS Pipelined ADC with 100dBFS SFDR[J].IEEE Journal of Solid-state Circuits,2010,45(12):2613-2622.
[3]FANG B N,WU J T.A 10-Bit 300-MS/s Pipelined ADC with Digital Calibration and Digital Bias Generation[J].IEEE Journal of Solid-state Circuits,2013,48(3):670-683.
[4]YANG C Y,LI F L,LI W T,et al.An 85mW 14-bit 150MS/s Pipelined ADC with 71.3dB Peak SNDR in 130nm CMOS[C]//Proceedings of the 2013IEEE Asian Solid-state Circuits Conference.Washington:IEEE Computer Society,2013:85-88.
[5]SETTERBERG B,POULTON K,RAY S,et al.A 14b2.5GS/s 8-way-interleaved Pipelined ADC with Background Calibration and Digital Dynamic Linearity Correction[C]//Digest of Technical Papers-IEEE International Solid-state Circuits Conference:56.Piscataway:IEEE,2013:466-467.
[6]ALI A M A,DINC H,BHORASKAR P,et al.A 14 Bit 1 GS/s RF Sampling Pipelined ADC with Background Calibration[J].IEEE Journal of Solid-state Circuits,2014,49(12):2857-2867.
[7]MIYAHARA Y,SANO M,KOYAMA K.et al.A 14b60MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity[J].IEEE Journal of Solid-state Circuits,2014,49(2):416-425.
[8]SEPKE T,FIORENZA J K,SODINI C G,et al.Comparator-based Switched-capacitor Circuits for Scaled CMOS Technologies[C]//Digest of Technical Papers-IEEE International Solid-state Circuits Conference.Piscataway:IEEE,2006:220-221.
[9]BROOKS L,LEE H S.A Zero-Crossing-Based 8-bit 200MS/s Pipelined ADC[J].IEEE Journal of Solid-state Circuits,2007,42(12):2677-2687.
[10]BERGLUND C N.Analog Performance Limitations of Charge Transfer Dynamic Shift Registers[J].IEEE Journal of Solid-state Circuits,1971,6(6):391-394.
[11]ANTHONY M,KOHLER E,KURTZE J,et al.A Process-scalable Low-power Charge-domain 13-bit Pipeline ADC[C]//IEEE Symposium on VLSI Circuits-Digest of Technical Papers.Piscataway:IEEE,2008:212-213.
[12]CHEN Z H,HUANG S R,ZHANG H,et al.A 27-mW 10-bit 125-MSPS Charge-domain Pipelined ADC with PVT Insensitive Boosted Charge Transfer[J].Journal of Semiconductors,2013,34(3):035009.
[13]CHEN Z H,QIAN H W,HUANG S R,et al.Low Power Time-interleaved 10-bit 250MSPS Charge Domain Pipelined ADC for IF Sampling[J].Journal of Semiconductors,2013,34(6):065005.
[14]SHIN C S,AHN G C.A 10-bit 100-MS/s Dual-channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique[J].IEEE Transactions on Circuits and Systems II:Express Briefs,2011,58(5):274-278.