一种10位250 MS/s电荷域流水线ADC
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摘要
提出了一种高速、低功耗、小面积的10位250MS/s模数转换器(ADC)。该ADC采用电荷域流水线结构,消除了高增益带宽积的跨导运算放大器,降低了ADC功耗。采用流水线逐级电荷缩减技术,降低了后级电路的电荷范围,减小了芯片面积。测试结果表明,在250 MS/s采样速率、9.9MHz输入正弦信号的条件下,该ADC的无杂散动态范围(SFDR)为64.4dB,信噪失真比(SNDR)为57.7dB,功耗为45mW。
A high speed,low power consumption and small size 10 bit 250 MS/s analog-to-digital converter(ADC)was presented.The high-gain-bandwidth operational transconductance amplifier(OTA)was eliminated and the power consumption of ADC was reduced by using the charge domain pipelined structure.The size of the ADC chip was reduced by scaling down the charge amount of the backend stages of sub-stage circuit with pipelined gradual charge reduction techniques.Measurement results showed that the spurious free dynamic range(SFDR)of 64.4 dB,signal-to-noise-and-distortion ration(SNDR)of 57.7 dB,power consumption of only 45 mW were implemented with input sinusoidal frequency of 9.9 MHz under the sampling rate of 250 MS/s.
A high speed,low power consumption and small size 10 bit 250 MS/s analog-to-digital converter(ADC)was presented.The high-gain-bandwidth operational transconductance amplifier(OTA)was eliminated and the power consumption of ADC was reduced by using the charge domain pipelined structure.The size of the ADC chip was reduced by scaling down the charge amount of the backend stages of sub-stage circuit with pipelined gradual charge reduction techniques.Measurement results showed that the spurious free dynamic range(SFDR)of 64.4 dB,signal-to-noise-and-distortion ration(SNDR)of 57.7 dB,power consumption of only 45 mW were implemented with input sinusoidal frequency of 9.9 MHz under the sampling rate of 250 MS/s.
引文
[1] CHEN Z H,HUANG S R,ZHANG H,et.al.A 27-mW 10-bit 125-MSPS charge-domain pipelined ADC with PVT insensitive boosted charge transfer[J].J Semicond,2013,34(3):035009-1-035009-9.
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[6] BROOKS L,LEE H S.A zero-crossing-based 8-bit200 MS/s pipelined ADC[J].IEEE J Sol Sta Circ,2007,42(12):2677-2687.
[7]HERSHBERG B,WEAVER S,SOBUE K,et al.Ring amplifiers for switched capacitor circuits[J].IEEE J Sol Sta Circ,2012,47(12):2928-2942.
[8] ANTHONY M,KOHLER E,KURTZE J,et al.A process-scalablelow-powercharge-domain13-bit pipeline ADC[C]∥IEEE Symp VLSI Circ.Honolulu,HI,USA.2008:222-223.
[9]黄嵩人,陈珍海,张鸿,等.用于电荷域流水线ADC的1.5位子级电路[J].西安电子科技大学学报,2016,43(6):170-175.
[2] CHEN Z H,QIAN H W,HUANG S R,et.al.A low power time-interleaved 10-bit 250 MSPS charge domain pipelined ADC for IF sampling[J].J Semicond,2013,34(6):065005-1-065005-8.
[3] ALI A M A,DILLON C,SNEED R,et al.A 14-bit125MS/s IF/RF sampling pipelined ADC with 100dB SFDR and 50fs jitter[J].IEEE J Sol Sta Circ,2006,41(8):1846-1855.
[4] DEVARAJAN S,SINGER L,DAN K,et al.A 16-bit,125 MS/s,385 mW,78.7 dB SNR CMOS pipeline ADC[J].IEEE J Sol Sta Circ,2009,44(12):3305-3313.
[5] SEPKE T,FIORENZA J K,SODINI C G,et al.Comparator-basedswitched-capacitorcircuitsfor scaled CMOS technologies[C]∥IEEE ISSCC.San Francisco,CA,USA.2006:220-221.
[6] BROOKS L,LEE H S.A zero-crossing-based 8-bit200 MS/s pipelined ADC[J].IEEE J Sol Sta Circ,2007,42(12):2677-2687.
[7]HERSHBERG B,WEAVER S,SOBUE K,et al.Ring amplifiers for switched capacitor circuits[J].IEEE J Sol Sta Circ,2012,47(12):2928-2942.
[8] ANTHONY M,KOHLER E,KURTZE J,et al.A process-scalablelow-powercharge-domain13-bit pipeline ADC[C]∥IEEE Symp VLSI Circ.Honolulu,HI,USA.2008:222-223.
[9]黄嵩人,陈珍海,张鸿,等.用于电荷域流水线ADC的1.5位子级电路[J].西安电子科技大学学报,2016,43(6):170-175.